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ISL6405
Data Sheet February 2003 FN9026
Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
The ISL6405 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of two antenna ports. The device is comprised of two independent currentmode boost PWMs and two low-noise linear regulators along with the circuitry required for 22Khz tone generation, modulation and I2C device interface. The device makes the total LNB supply design simple, efficient and compact with low external component count. Two independent current-mode boost converters provide the linear regulators with input voltages that are set to the final output voltages, plus typically 1.2V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drops across each linear pass element while permitting adequate voltage range for tone injection. The final regulated output voltages are available at two output terminals to support simultaneous operation of two antenna ports for dual tuners. The outputs for each PWM are set to 13V or 18V by independent voltage select commands (VSEL1, VSEL2) through the I2C bus. Additionally, to compensate for the voltage drop in the coaxial cable, the selected voltage may be increased by 1V with the line length compensation (LLC) feature. All the functions on this IC are controlled via the I2C bus by writing 8 bits on System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. Separate enable commands sent on the I2C bus provide independent standby mode control for each PWM and linear combination, disabling the output into shutdown mode. Each output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed The SEL18V pin with QFN package allows the 13V to 18V transition with an external pin, over-riding the I2C input.
Features
* Single Chip Power solution - True Dual Operation for 2-Tuner / 2-Dish Applications - Both Outputs May be Enabled Simultaneously at Maximum Power - Integrated DC-DC Converter and I2C Interface * Switch-Mode Power Converter for Lowest Dissipation - Boost PWMs with > 92% Efficiency - Selectable 13V or 18V Outputs - Digital Cable Length Compensation (1V) * I2C Compatible Interface for Remote Device Control - Registered Slave Address 0001 00XX - Full 3.3V / 5V Operation up to 400kHz * Built-In Tone Oscillator Factory Trimmed to 22kHz - Facilitates DiSEqCTM (EUTELSAT) Encoding * Internal Over-Temperature Protection and Diagnostics * Internal Overload and Overtemp Flags (Visible on I2C) * LNB Short-Circuit Protection and Diagnostics * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint * External Pins to Select 13V / 18V Options - Available with QFN Package Only
Applications
* LNB Power Supply and Control for Satellite Set-Top Box
References
Tech Brief 389 (TB389) - "PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages"; Available on the Intersil website, www.intersil.com
Ordering Information
PART NUMBER ISL6405EEB ISL6405ER TEMP. RANGE (oC) -20 to 85 -20 to 85 PACKAGE 28 LD EPSOIC 32 QFN PKG. NO. M28.3B L32.5x5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved
ISL6405
ISL6405 (EPSOIC) TOP VIEW
VSW2 1 COMP2 2 FB2 3 GATE2 4 PGND 2 5 CS2 6 SGND 7 BYPASS 8 PGND1 9 GATE1 10 CS1 11 FB1 12 COMP1 13 VSW1 14
28 VCC 27 CPVOUT 26 CPSWIN 25 CPSWOUT 24 TCAP2 23 DSQIN2
ISL6405EEB
22 VO2 21 AGND 20 VO1 19 DSQIN1 18 TCAP1 17 SCL 16 ADDRESS 15 SDA
ISL6405 (QFN) TOP VIEW
CPVOUT 26
32 PGND2 CS2 SGND SEL18V1 SEL18V2 BYP PGND1 GATE1 1 2 3 4 5 6 7 8 9 CS1
31
30
29
28
27
25 24 CPSWOUT 23 TCAP2 22 DSQIN2
CPSWIN 21 VO2 20 AGND 19 VO1 18 DSQIN1 17 TCAP1 16 SCL
COMP2
GATE2
VSW2
ISL6405ER
10 FB1
11 COMP1
12 VSW1
13 NC
14 SDA
VCC
FB2
NC
15 ADDR
2
Block Diagram
15 OLF1 ADDR COUNTER OVERCURRENT PROTECTION LOGIC SCHEME 1 PWM LOGIC 10 GATE1 Q S CLK1 SDA 9 PGND1 ISEL1 OLF ENT1 CS AMP 11 CS1 ILIM1 OTF LLC1 VSEL1 CLK1 OSC. 220kHZ VSEL2 CLK2 COMP2 LLC2 + EN1 ADDR SCL ISEL2 SDA SCL DCL OC1 16 17 OLF2 DCL OC2 CLK2 OVERCURRENT PROTECTION LOGIC SCHEME 2 PWM LOGIC Q S PGND2 5 COUNTER
GATE2
4
I2 C INTERFACE
ENT2 DCL
SLOPE COMPENSATION
13
COMP1 +
BAND GAP REF VOLTAGE BGV REF VOLTAGE ADJ1 TONE INJ CKT 1
BGV REF VOLTAGE ADJ2 TONE INJ CKT 2
/ 10 & WAVE SHAPING +
12
FB1 VREF1
22kHZ TONE
14
VSW1 VO2 + + ENT2
20
VO1
28
VCC
ON CHIP LINEAR UVLO POR SOFT-START BYPASS CPVOUT ENT1 27
7
SGND
DSQIN1
DSQIN2
TCAP1
TCAP2
AGND
INT 5V SOFT-START EN1/EN2
OTF
THERMAL SHUTDOWN
8
21
18
19
23
24
-
+
3
EN2
ILIM2
CS AMP CS2 6
SLOPE COMPENSATION
2
ISL6405
FB2 VREF2
3
VSW2
1
22
CHARGE PUMP
CPSWIN
26
CPSWOUT
25
Typical Application Schematic
VIN = 8V TO 14V
+C3 L1 D1 C4
+C14 L2
C1
+ C2 C20 Q1 28 VCC 7 SGND 10 GATE1 11 CS1 R1 R2 C12 9 PGND1 13 COMP1 12 FB1 14 VSW1 20 VO1 19 DSQIN1 23 DSQIN2 16 ADDRESS TCAP2 24 BYPASS 8 GATE2 4 CS2 6 PGND2 5 COMP2 2 FB2 3 VSW2 1 VO2 22 SCL 17 SDA 15 CPSWIN 26 CPSWOUT 25 CPVOUT 27 C9 C8 R3 C13 R3 R4 C6 Q2
D2 +C10 C11
4
C5 VO1 13V / 18V 18 TCAP1 C15 C16 21 AGND
ISL6405
C7
SCL SDA
C17
VO2 13V / 18V
ISL6405EEB
ISL6405
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V Logic Input Voltage Range (SDA, SCL, ENT) . . . . . . . . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Note 1, 2) JA (oC/W) JC (oC/W) EPSOIC Package (Note 1, 2). . . . . . . . 29 4 QFN Package (Note 1, 2). . . . . . . . . . . 34 6 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -40oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Temperature range . . . . . . . . . . . . . . . . . . -20oC to 85oC NOTE: The device junction temperature should be kept below 150oC. Thermal shut-down circuitry turns off the device if junction temperature exceeds +150oC typically.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Vcc = 12V, TA = -20oC to +85oC, unless otherwise noted.Typical values are at TA = 25oC.EN1=EN2=H, LLC1=LLC2=L, ENT1=ENT2=L, DCL=L, DSQIN1=DSQIN2=L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. SYMBOL TEST CONDITIONS EN1 = EN2 = L IIN EN1 = EN2 = LLC1 = LLC2 = VSEL1 = VSEL2 = ENT1 = ENT2 = H, No Load MIN 8 TYP 12 1.5 4.0 MAX 14 3.0 8.0 UNITS V mA mA
PARAMETER Operating Supply Voltage Range Standby Supply Current Supply Current UNDER VOLTAGE LOCKOUT Start Threshold Stop Threshold Start to Stop Hysteresis SOFT START COMP Rise Time (Note 3) Output Voltage (Note 4)
7.5 7.0 350 (Note 5) VO1 VO1 VO1 VO1 VO2 VO2 VO2 VO2 VSEL1 = L, LLC1 = L VSEL1 = L, LLC1 = H VSEL1 = H, LLC1 = L VSEL1 = H, LLC1 = H VSEL2 = L, LLC2 = L VSEL2 = L, LLC2 = H VSEL2 = H, LLC2 = L VSEL2 = H, LLC2 = H 12.74 13.72 17.64 18.62 12.74 13.72 17.64 18.62 425 775 ENT1/2 = H ENT1/2 = H ENT1/2 = H ENT1/2 = H Iout = 750mA (Note 5) 20.0 550 40 5
400 1024 13.0 14.0 18.0 19.0 13.0 14.0 18.0 19.0 4.0 4.0 50 100 850 900 20 22.0 680 50 8 1.2
7.95 7.55 500 13.26 14.28 18.36 19.38 13.26 14.28 18.36 19.38 40.0 60.0 80 200 550 950 24.0 900 60 14
V V mV Cycles V V V V V V V V mV mV mV mV mA mA ms ms kHz mV % s V
Line Regulation Load Regulation Dynamic Output Current Limiting Dynamic Overload Protection Off Time Dynamic Overload Protection On Time 22kHz TONE SECTION Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time Linear Regulator Drop-out Voltage
DVO1,DVO2 VIN = 8V to 14V; VO1, VO2 = 13V VIN = 8V to 14V; VO1, VO2 = 18V DVO1,DVO2 IO = 12mA to 350mA IO = 12mA to 750mA (Note 5) IMAX TOFF TON ftone Vtone dctone Tr, Tf DCL = L, ISEL1/2 = L DCL = L, ISEL1/2 = H (Note 5) DCL = L, Output Shorted (Note 5)
5
ISL6405
Electrical Specifications
Vcc = 12V, TA = -20oC to +85oC, unless otherwise noted.Typical values are at TA = 25oC.EN1=EN2=H, LLC1=LLC2=L, ENT1=ENT2=L, DCL=L, DSQIN1=DSQIN2=L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX 1.5V 3.5 1 (Note 5) IBIAS Static current mode, DCL = H AOL
GBP
PARAMETER DSQIN PIN DSQIN pin logic Low DSQIN pin Logic HIGH DSQIN pin Input Current CURRENT SENSE Current Limiting Threshold (max. input) Input Bias Current Over Current Threshold ERROR AMPLIFIER Open Loop Voltage Gain Gain Bandwidth Product PWM Maximum Duty Cycle Minimum Pulse Width OSCILLATOR Oscillator Frequency Thermal Shutdown Temperature Shutdown Threshold Temperature Shutdown Hysteresis NOTES: 3. Internal Digital Soft-start
UNITS V V A
150 325 70 10 90
200 700 400 88 93 20 220 150 20
250 500 240
mV nA mV dB MHz % nS kHz
(Note 5) (Note 5)
(Note 5) fo Fixed at (10)(ftone) (Note 5) (Note 5)
200
4. VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I2C bus. IO1 = IO2 = 350mA / 750mA. 5. Guaranteed by Design
Functional Pin Description
SYMBOL SDA SCL VSW1, 2 PGND1, 2 CS1, 2 SGND AGND TCAP1, 2 BYPASS DSQIN1, 2 Clock from I2C bus. Input of the linear post-regulator. Dedicated ground for the output gate driver of respective PWM. Current sense input; connect Rsc at this pin for desired over current value for respective PWM. Small signal ground for the IC. Analog ground for the IC. Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Bypass capacitor for internal 5V. When HIGH enables internal 22kHz modulation for LNB A and LNA B respectively, Use this pin for tone enable function for LNB A and LNB B. Main power supply to the chip. These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of driving the gate of a power FET. These outputs are actively held low when Vcc is below the UVLO threshold. Output voltage of LNB A and LNB B respectively. FUNCTION Bi-directional data from/to I2C bus.
Functional Pin Description (Continued)
SYMBOL ADDRESS COMP1, 2 FB1, 2 CPVOUT, CPSWIN, CPSWOUT SEL18V1, 2 FUNCTION Address pin to select two different addresses per voltage level at this pin. Error amp outputs used for compensation. Feedback pins for respective PWMs Charge pump connections.
When connected HIGH, this pin will change the output of the respective PWM to 18V. Only available on the QFN package option.
VCC GATE1, 2
VO1, 2
6
ISL6405 Functional Description
The ISL6405 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for two low-noise blocks (LNBs) are available simultaneously in any output configuration. The device utilizes built-in DC/DC step-converters that, from a single supply source ranging from 8V to 14V, generate the voltages that enable the linear post-regulators to work with a minimum of dissipated power. An undervoltage lockout circuit disables the circuit when VCC drops below a fixed threshold (7.5V typ). When the regulator blocks are active (EN1, EN2 = HIGH), the output can be logic controlled to be 13V or 18 V (typical) by mean of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC1/2 bit HIGH).
Output Timing
The programmed output voltage rise and fall times can be set by an internal 25k resistor and an external / internal capacitor located on the TCAP terminal. Although any value of capacitor is permitted, practical values are typically 0.1f to 1f. This feature only affects the turn-on and programmed voltage rise and fall times. This terminal can be left open if output voltage rise and fall time control is not required.
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSEqC (EUTELSAT) standards. No further adjustment is required. The 22kHz oscillator can be controlled either by the I2C interface (ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows immediate DiSEqC data encoding separately for each LNB. (Please see Note 1 at the end of this section.) All the functions of this IC are controlled via the I2C bus by writing to the system registers (SR1, SR2). The same registers can be read back, and two bits will report the diagnostic status. The internal oscillator operates the converters at ten times the tone frequency. The device offers full I2C compatible functionality, 3.3V or 5V, and up to 400kHz operation. If the Tone Enable (ENT1/2) bit is set LOW through I2C, then the DSQIN1/2 terminal activates the internal tone signal, modulating the dc output with a 0.3V, 22kHz, symmetrical waveform. The presence of this signal usually gives the LNB information about the band to be received. Burst coding of the 22kHz tone can be accomplished due to the fast response of the DSQIN1/2 input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols. When the ENT1/2 bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN1/2 pin logic status for the corresponding regulator channel (LNB-A or LNB-B). The ENT1/2 bit must be set LOW when the DSQIN1 and/or DSQIN2 pin is used for DiSEqC encoding.
Current Limiting
The current limiting block has two thresholds that can be selected by the ISEL bit of the SR and can work either statically (simple current clamp) or dynamically. The lower threshold is between 425mA and 530mA (ISEL = L), while the higher threshold is between 775mA and 925mA (ISEL = H). When the DCL (Dynamic Current Limiting) bit is set to LOW, the over current protection circuit works dynamically: as soon as an overload is detected, the output is shutdown for a time tOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time tON = 20ms. During tON, the device output will be current limited to 425mA or 775mA, depending on the ISEL bits. At the end of tON, if the overload is still detected, the protection circuit will cycle again through tOFF and tON. At the end of a full tON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical tON + tOFF time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF1/2 bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. The OLF1/2 bit will be LOW at the end of initial power-on soft-start.
Linear Regulator
The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25f. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN1, EN2 = LOW), both PWM power blocks are disabled. (i.e. when EN1 = 0, PWM1 is disabled, and when EN2 = 0, PWM2 is disabled). 7
Thermal Protection
This IC is protected against overheating. When the junction temperature exceeds 150C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW when the junction is cooled down to 135C (typical).
ISL6405
In over temperature conditions, the OTF Flag goes HIGH and the I2C data will be cleared. The user may need to monitor the I2C enable bits and OTF flag continuously and enable the chip, if I2C data is cleared. OTF conditions may also make the OLF flags go HIGH, when high capacitive loads are present or self-heating conditions occur at higher loads.
External Output Voltage Selection
The output voltage can be selected by the I2C bus. Additionally, the QFN package offers two pins (SEL18V1, SEL18V2) for independent 13V/18V output voltage selection. When using these pins, the I2C bits should be initialized to 13V status.
TABLE 1. I2C Bits 13V 14V xx xx SEL18V(1,2) LOW LOW HIGH HIGH O/P Voltage 13V 13V 18V 18V
8
ISL6405 I2C Bus Interface for ISL6405
(Refer to Philips I2C Specification, Rev. 2.1) Data transmission from main microprocessor to the ISL6405 and vice versa takes place through the two wire I2C bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stages of ISL6405 will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100Kbps in the standard-mode or up to 400Kbps in the fast-mode. The level of logic "0" and logic "1" is dependent of associated value of VDD as per electrical specification table. One clock pulse is generated for each data bit transferred. acknowledge bit. Data is transferred with the most significant bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 3). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.) The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6405 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.
SCL 1 SDA MSB START 2 8 9
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 1.
SDA
ACKNOWLEDGE FROM SLAVE
FIGURE 3. ACKNOWLEDGE ON THE I2C BUS
SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. This approach, though, is less protected from error and decreases the noise immunity.
FIGURE 1. DATA VALIDITY
START and STOP Conditions
As shown in Figure 2, START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
ISL6405 Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown below in Table 2: * A start condition (S) * A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I2C slave address for the ISL6405 is 0001 00XX)
SDA
SCL S START CONDITION P STOP CONDITION
* A sequence of data (1 byte + Acknowledge) * A stop condition (P)
TABLE 2. INTERFACE PROTOCOL S0 0 0 1 0 0 0 R/W ACK Data (8 bits) ACK P
FIGURE 2. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an
9
ISL6405
TABLE 3. SYSTEM REGISTER 1 (SR1) R,W SR1 R,W DCL R,W ISEL1 R,W ENT1 R,W LLC1 R,W VSEL1 R,W EN1 R OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2) R,W SR2 R,W ISEL2 R,W ENT2 R,W LLC2 R,W VSEL2 R,W EN2 R OTF R OLF2
System Register Format
* R, W = Read and Write bit * R = Read-only bit All bits reset to 0 at Power-On
Transmitted Data (I2C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1/SR2) of the ISL6405 via I2C bus. These will be written by the microprocessor as shown below. The spare bits of SR1/SR2 can be used for other functions.
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR 0 0 0 0 0 0 0 0 0 0 0 0
DCL
ISEL1
ENT1
LLC1 0 0 0 1 1
VSEL1 0 0 1 0 1
EN1 1 1 1 1 1 1 1 1 1 1 1
OLF1 SR1 is selected
Function
Vout1 = 13V, Vboost1 = 13V + Vdrop Vout1 = 18V, Vboost1 = 18V + Vdrop Vout1 = 14V, Vboost1 = 14V + Vdrop Vout1 = 19V, Vboost1 = 19V + Vdrop 22kHz tone is controlled by DSQENT1 pin 22kHz tone is ON, DSQENT1 is disabled Iout1 = 425mA max. Iout1 = 775mA max. Dynamic current limit NOT selected Dynamic current limit selected PWM and Linear for channel 1 disabled
0 1 0 1 1 0 X X X X X
0
SR 1 1 1 1 1 1 1 1 1 1
ISEL2
ENT2
LLC2
VSEL2
EN2 X
OTF
OLF2 X X X X X X X X X X SR2 is selected
Function
0 0 1 1 0 1 0 1 X X X
0 1 0 1
1 1 1 1
X X X X X X X X
Vout2 = 13V, Vboost2 = 13V + Vdrop Vout2 = 18V, Vboost2 = 18V + Vdrop Vout2 = 14V, Vboost2 = 14V + Vdrop Vout2 = 19V, Vboost2 = 19V + Vdrop 22kHz tone is controlled by DSQENT2 pin 22kHz tone is ON, DSQENT2 is disabled Iout2 = 425mA max. Iout2 = 775mA max. PWM and Linear for channel 2 disabled
X
0
X
10
ISL6405
Received Data (I2C bus READ MODE)
The ISL6405 can provide to the master a copy of the system register information via the I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following Master generated clock bits, the ISL6405 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: * Acknowledge the reception, starting in this way the transmission of another byte from the ISL6405. * Not acknowledge, stopping the read mode communication. While the whole register is read back by the microprocessor, only the two read-only bits, OLF and OTF, convey diagnostic information about the ISL6405. After selection of SR1/SR2
TABLE 6. READING SYSTEM REGISTERS DCL ISEL1/2 ENT1/2 LLC1/2 VSEL1/1 EN1/2 OTF2 0 1 0 1 OLF1/2 Function TJ <= 135C, normal operation TJ > 150C, power blocks disabled IOUT < IMAX, normal operation IOUT > IMAX, overload protection triggered
These bits are read as they were after the last write operation.
Power-On I2C Interface Reset
The I2C interface built into the ISL6405 is automatically reset at power-on. The I2C interface block will receive a Power OK logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the interface will not respond to any I2C commands and the system register SR1 and SR2 are initialized to all zeros, thus keeping the power blocks disabled. Once the Vcc rises above UVLO, the POWER OK signal given to the I2C interface block will be HIGH, the I2C interface becomes operative and the SRs can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the PowerOn reset circuit. (I2C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I2C data for that PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I2C interface address is 0001000, but, it is possible to choose between two different addresses simply by setting this pin at one of the two fixed voltage levels as shown in Table 8.
TABLE 7. ADDRESS PIN CHARACTERISTICS VADDR VADDR-1 "0001000" VADDR-2 "0001001" Minimum 0V 2.7V Typical Maximum 2V 5V
I2C Electrical Characteristics
TABLE 8. I2C SPECIFICATIONS Parameter Input Logic High, VIH Input Logic Low, VIL Input Logic Current, IIL SCL Clock Frequency Test Condition SDA, SCL SDA, SCL SDA, SCL; 0.4V11
ISL6405 Small Outline Exposed Pad Plastic Packages (EPSOIC)
N INDEX AREA E -B1 2 3 H 0.25(0.010) M BM
M28.3B
28 LEAD WIDE BODY SMALL OUTLINE EXPOSED PAD PLASTIC PACKAGE INCHES SYMBOL A A1
TOP VIEW L SEATING PLANE -AD -CA h x 45o
MIN 0.091 0.001 0.014 0.0091 0.701 0.292
NOMINAL 0.050 BSC
MAX 0.099 0.005 0.019 0.0125 0.711 0.299
NOTES 9 3 4 -
B C D E e H
0.400 0.010 0.024
28
0.410 0.016 0.040
5 6 7
A1 0.10(0.004) C
h L N
e
B 0.25(0.010) M SIDE VIEW C AM BS
P P1
0 0.180 0.156
5 0.214 0.190
8 0.218 0.194
11 11 Rev. 0 5/02
1
2
3
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95.
P1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
N P BOTTOM VIEW
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: INCH. 11. Dimensions "P" and "P1" are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count body size.
12
ISL6405 Quad Flat No-Lead Plastic Package (QFN)
2X A D D/2 D1 0.15 C A
L32.5x5
32 PAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VHHD-2 ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75 BSC 2.95 3.10 0.50 BSC 0.25 0.30 0.40 32 8 8 0.60 12 0.50 3.25 3.25 0.30 MAX 0.90 0.05 0.70 NOTES 5,8 7,8 7,8 8 2 3 3 Rev. 0 6/01 NOTES:
D1/2 2X 6 0.50 DIA. 1 2 3 N E1/2 E1 E/2 E 0.15 C B
A A1 A2 A3 b D
0.15 C B 2X 0.15 C A 2X 0 A2 A C NX 0.05 C SEATING PLANE SIDE VIEW NX b 4X P D2 D2 2N 4X P 1 2 3 E2 7 NX L 8 e (Nd-1)Xe REF. BOTTOM VIEW C L 5 NX b C A1 C L C E2/2 8 (Ne-1)Xe REF. 5 0.10 M C A B 7 8 NX k A3 A1 TOP VIEW B
D1 D2 E E1 E2 e k L N Nd Ne P
1. Dimensioning and tolerancing per ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd is the number of terminals in the X direction, and Ne is the number of terminals in the Y direction. 4. Controlling dimension: Millimeters. Converted dimensions to inches are not necessarily exact. Angles are in degrees. 5. Dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip. 6. The Pin #1 identifier exists on the top surface as an indentation mark in the molded body. 7. Dimensions D2 and E2 are the maximum exposed pad dimensions for improved grounding and thermal performance. 8. Nominal dimensions provided to assist with PCB Land Pattern Design efforts, see Technical Brief TB389.
SECTION "C-C" e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE e
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13

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